Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-54 Freescale Semiconductor
Table 14-64 describes the PCI Express uncorrectable error status register fields.
14.4.5.3 PCI Express Uncorrectable Error Mask Register
The PCI Express uncorrectable error mask register is shown in Figure 14-68. An error is masked if the
corresponding mask bit in this register is set.
Table 14-64. PCI Express Uncorrectable Error Status Register Fields Description
Bits Name Description
31–21 — Reserved
20 URE Unsupported request error status
19 ECRCE ECRC error status
18 MTLP Malformed TLP status
17 RXO Receiver overflow status
16 UC Unexpected completion status
15 CA Completer abort status
14 CTO Completion timeout status
13 FCPE Flow control protocol error status
12 PTLP Poisoned TLP status
11–5 — Reserved
4 DLPE Data link protocol error status
3–1 — Reserved
0 TE Training error status
Offset 0x108 Access: Read/Write
31 21 20 19 18 17 16
R
— UREM ECRCEM MTLPM RXOM UCM
W
Reset All zeros
15 14 13 12 11 5 4 3 1 0
R
CAM CTOM FCPEM PTLPM — DLPEM — TEM
W
Reset All zeros
Figure 14-68. PCI Express Uncorrectable Error Mask Register