Information

Overview

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 1-15

1.2.9 I

C Interface

The inter-IC (IIC or I

C) bus is a two-wire—serial data (SDA) and serial clock (SCL)— bidirectional

serial bus that provides a simple, efficient method of data exchange between the system and other devices,

such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs. The two-wire

bus minimizes the interconnections between devices. The synchronous, multi-master bus of the I

C allows

the connection of additional devices to the bus for expansion and system development.

The I

C controller is a true multi-master bus, which includes collision detection and arbitration that

prevents data corruption if two or more masters attempt to control the bus simultaneously. This feature

allows for complex applications with multiprocessor control. The I

C controller consists of a

transmitter/receiver unit, clocking unit, and control unit. The I

C unit supports general broadcast mode and

on-chip filtering rejects spikes on the bus.

The I

C interface includes the following features:

• Two-wire interface

• Multi-master operational

• Arbitration lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• Bus busy detection

• Software-programmable clock frequency

• Software-selectable acknowledge bit

• On-chip filtering for spikes on the bus

• Address broadcasting supported

1.2.10 General Purpose DMA Controller

The direct memory access (DMA) is capable of performing complex data transfers with minimal

intervention from a host processor via two programmable channels. The hardware architecture includes a

DMA engine, which performs source and destination address calculations, and the actual data movement

operations, along with a local memory containing the transfer control descriptors (TCD) for the channels.

This SRAM-based implementation is utilized to minimize the overall module size.

The DMA is a highly programmable data transfer engine that has been optimized to minimize the required

intervention from the host processor. It is intended for use in applications where the data size to be

transferred is statically known, and is not defined within the data packet itself. The DMA hardware

supports:

• Single design with two channels (Tx and Rx)

• 32-byte transfer control descriptor per channel stored in local memory

• 32 bytes of data registers, used as temporary storage to support burst transfers