Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-50 Freescale Semiconductor
Table 14-59 describes the PCI Express MSI message control register fields.
14.4.4.22 PCI Express MSI Message Address Register (EP Mode Only)
The PCI Express MSI message address register is shown in Figure 14-62.
Table 14-60 describes the PCI Express MSI message address register fields.
14.4.4.23 PCI Express MSI Message Upper Address Register (EP Mode Only)
The PCI Express MSI message upper address register is shown in Figure 14-63.
Table 14-61 describes the PCI Express MSI message upper address register fields.
Table 14-59. PCI Express MSI Message Control Register Fields Description
Bits Name Description
15–8 — Reserved
7 64AC 64-bit address capable
6–4 MME Multiple message enable
3–1 MMC Multiple message capable
0 MSIE MSI enable
Offset 0x074 Access: Read/Write
31 210
R
Message Address
00
W
Reset All zeros
Figure 14-62. PCI Express MSI Message Address Register
Table 14-60. PCI Express MSI Message Address Register Fields Description
Bits Name Description
31–2 Message Address System-specified message address
1–0 00 Always returns 00 on reads; write operations have no effect.
Offset 0x078 Access: Read/Write
31
R
Message Upper Address
W
Reset All zeros
Figure 14-63. PCI Express MSI Message Upper Address Register
Table 14-61. PCI Express MSI Message Upper Address Register Fields Description
Bits Name Description
31–0 Message Upper Address System-specified message upper address