Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-45
14.4.4.14 PCI Express Link Status Register
The PCI Express link status register is shown in Figure 14-54.
Table 14-52 describes the PCI Express link status register fields.
14.4.4.15 PCI Express Slot Capabilities Register
The PCI Express slot capabilities register is shown in Figure 14-55. For End Point applications
implementing a slot, the content of this register can be modified using the PCI Express Slot Capabilities
Update Register as described in Section 14.4.6.11, “PCI Express Slot Capabilities Update Register
(PEX_SLCAP_UPDATE).”
Offset 0x05E Access: Read-only
15 13 12 11 10 9 4 3 0
R — SCC LT — NEG_LINK_W LINK_SP
W
Reset0000000000010001
Figure 14-54. PCI Express Link Status Register
Table 14-52. PCI Express Link Status Register Fields Description
Bits Name Description
15–13 — Reserved
12 SCC Slot clock configuration
11 LT Link training
10 — Reserved.
9–4 NEG_LINK_W Negotiated link width
3–0 LINK_SP Link speed
Offset 0x060 Access: Read-only
31 19 18 17 16
R Physical Slot Number — SPLS
W
Reset 0x0000
1514 76543 2 10
R — SPLV HPC HPS PIP AIP MRLSP PCP ABP
W
Reset 0x07C0
Figure 14-55. PCI Express Slot Capabilities Register