Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-44 Freescale Semiconductor
Table 14-50 describes the PCI Express link capabilities register fields.
14.4.4.13 PCI Express Link Control Register
The PCI Express link control register is shown in Figure 14-53.
Table 14-51 describes the PCI Express link control register fields.
Table 14-50. PCI Express Link Capabilities Register Fields Description
Bits Name Description
31–24 Port Number
23–18 — Reserved
17–15 L1_EX_LAT L1 exit latency. 0b111 indicates more than 64 microseconds
14–12 L0s_EX_LAT L0s exit latency. 0b101 indicates 1024 ns to less than 2048 ns
11–10 ASPM Active state power management (ASPM) Support, L0s Entry Supported
9–4 MAX_LINK_W Maximum link width
0b000001 1
3–0 MAX_LINK_SP Maximum link speed, 0b0001 indicates 2.5 Gb/s
Offset 0x05C Access: Read/Write
15 87 6543210
R
— EXT_SYNC CCC RL LD RCB — ASPM_CTL
W
Reset All zeros
Figure 14-53. PCI Express Link Control Register
Table 14-51. PCI Express Link Control Register Fields Description
Bits Name Description
15–8 — Reserved
7 EXT_SYNC Extended synch
6 CCC Common clock configuration
5 RL Retrain link
4 LD Link disable
3 RCB Read completion boundary
2—Reserved
1–0 ASPM_CTL Active state power management (ASPM) control