Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-43
14.4.4.11 PCI Express Device Status Register
The PCI Express device status register is shown in Figure 14-51.
Table 14-49 describes the PCI Express device status register fields.
14.4.4.12 PCI Express Link Capabilities Register
The PCI Express link capabilities register is shown in Figure 14-52. Note that for End Point mode, some
of these fields can indirectly be set using the PCI Express Link Capabilities Update Register
(PEX_LINKCAP_UPDATE). See Section 14.4.6.10, “PCI Express Link Capabilities Update Register
(PEX_LINKCAP_UPDATE),” for more details.
Offset 0x056 Access: Mixed
15 6543210
R
—
TP APD URD FED NFED CED
W
w1c w1c w1c w1c
Reset All zeros
Figure 14-51. PCI Express Device Status Register
Table 14-49. PCI Express Device Status Register Fields Description
Bits Name Description
15–6 — Reserved
5 TP Transactions pending
4 APD AUX power detected
3 URD Unsupported request detected
2 FED Fatal error detected
1 NFED Non-fatal error detected
0 CED Correctable error detected
Offset 0x058 Access: Read-only
31 24 23 18 17 16
R Port Number — L1_EX_LAT...
W
Reset0000000000000 0 1 1
15 14 12 11 10 9 4 3 0
R ... L0s_EX_LAT ASPM MAX_LINK_W MAX_LINK_SP
W
Reset1101010000010 0 0 1
Figure 14-52. PCI Express Link Capabilities Register