Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-42 Freescale Semiconductor
14.4.4.10 PCI Express Device Control Register
The PCI Express device control register is shown in Figure 14-50.
Table 14-48 describes the PCI Express device control register fields.
4–3 PHAN_FCT Phantom functions supported
2–0 MAX_PL_SIZE_SUP Maximum payload size supported. 000 = 128 bytes
Offset 0x054 Access: Read/write
15 14 12 11 10 9 8 7 5 4 3 2 1 0
R
— MAX_READ_SIZE NSE APE PFE ETE MAX_PAYLOAD_SIZE RO URR FER NFER CER
W
Reset00101000 0 0 0 10000
Figure 14-50. PCI Express Device Control Register
Table 14-48. PCI Express Device Control Register Fields Description
Bits Name Description
15 — Reserved
14–12 MAX_READ_SIZE Maximum read request size
11 NSE No snoop enable
10 APE AUX power PM enable
9 PFE Phantom functions enable
8 ETE Extended tag field enable
7–5 MAX_PAYLOAD_SIZE Maximum payload size
4 RO Relaxed ordering
3 URR Unsupported request reporting
2 FER Fatal error reporting
1 NFER Non-fatal error reporting
0 CER Correctable error reporting
Table 14-47. PCI Express Device Capabilities Register Fields Description (continued)
Bits Name Description