Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-41
14.4.4.9 PCI Express Device Capabilities Register
The PCI Express device capabilities register is shown in Figure 14-49. Note that for End Point mode some
of these fields can be set indirectly, using the PCI Express Device Capabilities Update Register. See
Section 14.4.6.9, “PCI Express Device Capabilities Update Register (PEX_DEVCAP_UPDATE),” for
additional details.
Table 14-47 describes the PCI Express capabilities register fields.
7–4 Device/Port Type 0100 (RC mode)
0000 (EP mode)
3–0 Version Indicates PCI-SIG defined PCI Express capability structure version number.
0x1identifies version 1.0a.
Offset 0x050 Access: Read-only
31 28 27 26 25 18 17 16
R — CSPLS CSPLV —
W
Reset0000000000000 0 0 0
15 14 13 12 11 9 8 6 5 4 3 2 0
R — PIP AIP ABP EP_L1_LAT EP_L0s_LAT ET PHAN_FCT MAX_PL_SIZE_SUP
W
Reset0000000000000 0 0 0
Figure 14-49. PCI Express Device Capabilities Register
Table 14-47. PCI Express Device Capabilities Register Fields Description
Bits Name Description
31–28 — Reserved
27–26 CSPLS Captured slot power limit scale
25–18 CSPLV Captured slot power limit value
17–15 — Reserved
14 PIP Power indicator present
13 AIP Attention indicator present
12 ABP Attention button present
11–9 EP_L1_LAT Endpoint L1 acceptable latency
8–6 EP_L0s_LAT Endpoint L0s acceptable latency
5 ET Extended tag field supported
Table 14-46. PCI Express Capabilities Register Fields Description (continued)
Bits Name Description