Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-40 Freescale Semiconductor
Table 14-44 describes the PCI Express capability ID register fields.
14.4.4.7 PCI Express Next Capabilities Pointer Register
The PCI Express next capabilities pointer register is shown in Figure 14-47.
Table 14-45 describes the PCI Express next capabilities pointer fields.
14.4.4.8 PCI Express Capabilities Register
The PCI Express capabilities register is shown in Figure 14-48.
Table 14-46 describes the PCI Express capabilities register fields.
Table 14-44. PCI Express Capability ID Register Fields Description
Bits Name Description
7–0 PCI Express Capability ID PCI Express = 0x10
Offset 0x04D Access: Read-only
7 0
R
W
Reset 0 1
1
1
1
1
1
0000
1 The reset value of 0b0111_0000 is only true in EP mode. In RC mode, the reset values should be 0b0000_0000.
Figure 14-47. PCI Express Next Capabilities Pointer
Table 14-45. PCI Express Next Capabilities Pointer Fields Description
Bits Name Description
7–0 Points to the PCI Express MSI capability registers. The reset value is 0x70 in EP mode and 0x00 in RC mode.
Offset 0x04E Access: Read-only
15 14 13 8 7 4 3 0
R — Interrupt Message Number Slot Device/Port Type Version
W
Reset000000000n 000001
Figure 14-48. PCI Express Capabilities Register
Table 14-46. PCI Express Capabilities Register Fields Description
Bits Name Description
15–14 — Reserved
13–9 Interrupt Message Number This device supports only a single MSI number.
8 Slot Slot Implemented (RC mode only)