Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-38 Freescale Semiconductor
14.4.4.3 PCI Express Power Management Capabilities Register
The PCI Express power management capabilities register is shown in Figure 14-43.
Table 14-41 describes the PCI Express power management capabilities register fields.
14.4.4.4 PCI Express Power Management Status and Control Register
The PCI Express power management status and control register is shown in Figure 14-44.
Table 14-42 describes the PCI Express power management status and control register fields.
Offset 0x046 Access: Read-only
15 11 10 9 8 6 5 4 3 2 0
R PME Support D2 D1 AUX Curr DSI — PME CLK Version
W
Reset011111100000 0 010
Figure 14-43. PCI Express Power Management Capabilities Register
Table 14-41. PCI Express Power Management Capabilities Register Fields Description
Bits Name Description
15–11 PME Support For a device, this 5-bit field indicates the power states in which the device may generate a PME. PME
can be issues from D0, D1, D2 and D3hot.
10 D2 D2 power state is supported.
9 D1 D1 power state is supported.
8–6 AUX Curr AUX Current. Vaux and D3cold is not supported by this device.
5 DSI A Device Specific Initialization is not required.
4—Reserved
3 PME CLK Does not apply to PCI Express
2–0 Version 0x02 indicates compatibility to the PCI Express Base Specification, Rev. 1.0a
Offset 0x048 Access: Mixed
15 14 13 12 9 8 7 2 1 0
R PME_STAT Data Scale
Data Select
PME_EN —
Power State
Ww1c
Sticky
Reset All zeros
Figure 14-44. PCI Express Power Management Status and Control Register
Table 14-42. PCI Express Power Management Status and Control Register Fields Description
Bits Name Description
15 PME_STAT PME Status. This bit is set when PME is generated. Writing a “1” to this bit will clear it. Writing a “0” has
no effect.
14–13 Data Scale —
12–9 Data Select —