Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-35
14.4.3.17 PCI Express Interrupt Line Register
The PCI Express interrupt line register, shown in Figure 14-38, is used by device drivers and OS software
to communicate interrupt line routing information. Values in this register are programmed by system
software and are system-specific.
Table 14-37 describes the PCI Express capabilities pointer register fields.
14.4.3.18 PCI Express Bridge Control Register (RC Mode Only)
The PCI Express bridge control register is shown in Figure 14-39.
Table 14-38 describes the PCI Express bridge control register fields.
Offset 0x03C Access: Read/Write
7 0
R
Interrupt Line
W
Reset All zeros
Figure 14-38. PCI Express Interrupt Line Register
Table 14-37. PCI Express Interrupt Line Register Fields Description
Bits Name Description
7–0 Interrupt Line Communicates interrupt line routing information.
Offset 0x03E Access: Read/Write
15 7 6 5 4 3 2 1 0
R
— Scnd_RST — VGA_EN ISA_EN SERR_EN PER
W
Reset All zeros
Figure 14-39. PCI Express Bridge Control Register
Table 14-38. PCI Express Bridge Control Register Fields Description
Bits Name Description
15–7 — Reserved
6 Scnd_RST Secondary bus reset
5–4 — Reserved
3 VGA_EN VGA enable
2 ISA_EN ISA enable
1 SERR_EN SERR enable. Controls the propagation of ERR_COR, ERR_NONFATAL, and ERR_FATAL responses
received on the secondary side. If this bit is set and an error message is received from the secondary
side, the ERRD bit in PEX_CSMISR is set.
0 PER Parity error response.