Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-34 Freescale Semiconductor
14.4.3.15 PCI Express I/O Limit Upper 16-Bit Register (RC Mode Only)
Note that this device does not support inbound I/O transactions. The I/O limit upper 16-bit register is
shown in Figure 14-36.
Table 14-35 describes the I/O limit upper 16-bit register fields.
14.4.3.16 PCI Express Capabilities Pointer Register
The PCI Express capabilities pointer, shown in Figure 14-37, identifies additional functionality supported
by the device.
Table 14-36 describes the PCI Express capabilities pointer register fields.
Offset 0x032 Access: Read-only
15 0
R I/O Limit Upper 16 Bits
W
Reset All zeros
Figure 14-36. PCI Express I/O Limit Upper 16-Bit Register
Table 14-35. PCI Express I/O Limit Upper 16-Bit Register Fields Description
Bits Name Description
15–0 I/O Limit Upper
16 Bits
Specifies bits 31–16 of the I/O space ending address when the address decode type field in the I/O
limit register is 0x01.
Offset 0x034 Access: Read-only
7 0
R Capabilities Pointer
W
Reset01000100
Figure 14-37. PCI Express Capabilities Pointer Register
Table 14-36. PCI Express Capabilities Pointer Register Fields Description
Bits Name Description
7–0 Capabilities
Pointer
Provides the offset (0x44) for additional PCI-compatible registers above the common 64-byte header.
Refer to Section 14.4.4, “PCI Express-Compatible Device-Specific Configuration Space Registers.”