Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-33
Table 14-32 describes the PCI Express prefetchable memory base upper 32-bit register fields.
14.4.3.13 PCI Express Prefetchable Limit Upper 32-Bit Register (RC Mode Only)
The PCI Express prefetchable memory base upper 32-bit register is shown in Figure 14-34.
Table 14-33 describes the PCI Express prefetchable memory limit upper 32-bit register fields.
14.4.3.14 PCI Express I/O Base Upper 16-Bit Register (RC Mode Only)
Note that this device does not support inbound I/O transactions. The I/O base upper 16-bit register is
shown in Figure 14-35.
Table 14-34 describes the I/O base upper 16 bits register fields.
Table 14-32. PCI Express Prefetchable Base Upper 32-Bit Register Fields Description
Bits Name Description
31–0 PF Base Upper
32 Bits
Specifies bits 64–32 of the prefetchable memory space start address when the address decode type
field in the prefetchable memory base register is 0x01.
Offset 0x02C Access: Read/Write
31
R
PF Limit Upper 32 Bits
W
Reset All zeros
Figure 14-34. PCI Express Prefetchable Limit Upper 32-Bit Register
Table 14-33. PCI Express Prefetchable Limit Upper 32-Bit Register Fields Description
Bits Name Description
31–0 PF Limit Upper
32 Bits
Specifies bits 64–32 of the prefetchable memory space ending address when the address decode
type field in the prefetchable memory limit register is 0x01.
Offset 0x030 Access: Read-only
15 0
R I/O Base Upper 16 Bits
W
Reset All zeros
Figure 14-35. PCI Express I/O Base Upper 16-Bit Register
Table 14-34. PCI Express I/O Base Upper 16-Bit Register Fields Description
Bits Name Description
15–0 I/O Base Upper
16 Bits
Specifies bits 31–16 of the I/O space start address when the address decode type field in the I/O
base register is 0x01.