Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-32 Freescale Semiconductor
Table 14-30 describes the prefetchable memory base register fields.
14.4.3.11 PCI Express Prefetchable Memory Limit Register (RC Mode Only)
The PCI Express prefetchable memory limit register is shown in Figure 14-32.
Table 14-31 describes the prefetchable memory limit register fields.
14.4.3.12 PCI Express Prefetchable Base Upper 32-Bit Register (RC Mode Only)
The PCI Express prefetchable memory base upper 32-bit register is shown in Figure 14-33.
Table 14-30. PCI Express Prefetchable Memory Base Register Fields Description
Bits Name Description
15–4 PF Memory Base Specifies bits 31–20 of the prefetchable memory space start address.
3–0 Address
Decode Type
Number of prefetchable memory address bits.
0x00 32-bit memory address decode
0x01 64-bit memory address decode
All other settings reserved.
Offset 0x026 Access: Read/Write
15 43 0
R
PF Memory Limit
Address Decode Type
W
Reset All zeros
Figure 14-32. PCI Express Prefetchable Memory Limit Register
Table 14-31. PCI Express Prefetchable Memory Limit Register Fields Description
Bits Name Description
15–4 PF Memory Limit Specifies bits 31–20 of the prefetchable memory space ending address.
3–0 Address
Decode Type
Specifies the number of prefetchable memory address bits.
0x00 32-bit memory address decode
0x01 64-bit memory address decode
All other settings reserved.
Offset 0x028 Access: Read/Write
31
R
PF Base Upper 32 Bits
W
Reset All zeros
Figure 14-33. PCI Express Prefetchable Base Upper 32-Bit Register