Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-31
Table 14-28 describes the memory base register fields.
14.4.3.9 PCI Express Memory Limit Register (RC Mode Only)
The memory limit register is shown in Figure 14-30.
Table 14-29 describes the memory base register fields.
14.4.3.10 PCI Express Prefetchable Memory Base Register (RC Mode Only)
The prefetchable memory base register is shown in Figure 14-31.
Table 14-28. PCI Express Memory Base Register Fields Description
Bits Name Description
15–4 Memory
Base
Specifies bits 31–20 of the non-prefetchable memory space start address. Typically used for specifying
memory-mapped I/O space.
Note: Inbound posted transactions hitting into the mem base/limit range are ignored; inbound non-posted
transactions hitting into the mem base/limit range results in an unsupported request response.
3–0 — Reserved
Offset 0x022 Access: Read/Write
15 43 0
R
Memory Limit
—
W
Reset All zeros
Figure 14-30. PCI Express Memory Limit Register
Table 14-29. PCI Express Memory Limit Register Fields Description
Bits Name Description
15–4 Memory
Limit
Specifies bits 31–20 of the non-prefetchable memory space ending address. Typically used for specifying
memory-mapped I/O space.
Note: Inbound posted transactions hitting into the mem base/limit range are ignored; inbound non-posted
transactions hitting into the mem base/limit range result in an unsupported request response.
3–0 — Reserved
Offset 0x024 Access: Read/Write
15 43 0
R
PF Memory Base
Address Decode Type
W
Reset All zeros
Figure 14-31. PCI Express Prefetchable Memory Base Register