Information
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-30 Freescale Semiconductor
14.4.3.7 PCI Express Secondary Status Register (RC Mode Only)
The PCI Express secondary status register is shown in Figure 14-28. Note that the errors in this register
can be masked by corresponding bits in the secondary status interrupt mask register
(PEX_SS_INTR_MASK) and that by default all the errors are masked. See Section 14.4.8.3, “Secondary
Status Interrupt Mask Register (PEX_SS_INTR_MASK) (RC Mode Only),” for more information.
Table 14-27 describes the PCI Express secondary status register fields.
14.4.3.8 PCI Express Memory Base Register (RC Mode Only)
The memory base register is shown in Figure 14-29.
Offset 0x01E Access: Mixed
15 14 13 12 11 10 9 8 7 0
R DPE SSE RMA RTA STA
—
MDPE
—
W w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 14-28. PCI Express Secondary Status Register
Table 14-27. PCI Express Secondary Status Register Fields Description
Bits Name Description
15 DPE Detected parity error. This bit is set when the secondary side receives a poisoned TLP regardless of the
state of the parity error response bit.
14 SSE Signaled system error. This bit is set when a device sends a ERR_FATAL or ERR_NONFATAL message if
the SERR enable bit in the command register is set to enable reporting.
13 RMA Received master abort. This bit is set when the secondary side receives an unsupported request (UR)
completion.
12 RTA Received target abort. This bit is set when the secondary side receives a completer abort (CA) completion.
11 STA Signaled target abort. This bit is set when the secondary side issues a CA completion.
10–9 — Reserved.
8 MDPE Master data parity error. This bit is set when the parity error response bit is set and the secondary side
requestor receives a poisoned completion or poisons a write request. If the parity error response bit is
cleared, this bit is never set.
7–0 — Reserved
Offset 0x020 Access: Read/Write
15 43 0
R
Memory Base
—
W
Reset All zeros
Figure 14-29. PCI Express Memory Base Register