Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-29
14.4.3.5 PCI Express I/O Base Register (RC Mode Only)
Note that this device does not support inbound I/O transactions. The I/O base register is shown in
Figure 14-26.
Table 14-25 describes the I/O base register fields.
14.4.3.6 PCI Express I/O Limit Register (RC Mode Only)
Note that this device does not support inbound I/O transactions. The I/O limit register is shown in
Figure 14-27.
Table 14-26 describes the I/O limit register fields.
Offset 0x01C Access: Read-only
7430
R I/O Start Address Address Decode Type
W
Reset All zeros
Figure 14-26. PCI Express I/O Base Register
Table 14-25. PCI Express I/O Base Register Fields Description
Bits Name Description
7–4 I/O Start Address Specifies bits 15–12 of the I/O space start address
3–0 Address
Decode Type
Specifies the number of I/O address bits.
0x00 16-bit I/O address decode
0x01 32-bit I/O address decode
All other settings reserved.
Offset 0x01D Access: Read-only
7430
R I/O Limit Address Address Decode Type
W
Reset All zeros
Figure 14-27. PCI Express I/O Limit Register
Table 14-26. PCI Express I/O Limit Register Fields Description
Bits Name Description
7–4 I/O Limit Address Specifies bits 15–12 of the I/O space ending address
3–0 Address
Decode Type
Specifies the number of I/O address bits.
0x00 16-bit I/O address decode
0x01 32-bit I/O address decode
All other settings reserved.