Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-28 Freescale Semiconductor
14.4.3.2 PCI Express Secondary Bus Number Register (RC Mode Only)
The secondary bus number register is shown in Figure 14-24.
Table 14-23 describes the secondary bus number register fields.
14.4.3.3 PCI Express Subordinate Bus Number Register (RC Mode Only)
The subordinate bus number register is shown in Figure 14-25.
Table 14-24 describes the subordinate bus number register fields.
14.4.3.4 PCI Express Secondary Latency Timer Register (RC Mode Only)
The secondary latency timer register does not apply to PCI Express. It must be read-only and return all
zeros when read.
Offset 0x019 Access: Read/Write
7 0
R
Secondary Bus Number
W
Reset All zeros
Figure 14-24. PCI Express Secondary Bus Number Register
Table 14-23. PCI Express Secondary Bus Number Register Fields Description
Bits Name Description
7–0 Secondary
Bus Number
Bus that is directly connected to the downstream interface. Note that this register is programmed
during system enumeration; in RC mode, this register is typically programmed to 0x01.
Offset 0x01A Access: Read/Write
7 0
R
Subordinate Bus Number
W
Reset All zeros
Figure 14-25. PCI Express Subordinate Bus Number Register
Table 14-24. PCI Express Subordinate Bus Number Register Fields Description
Bits Name Description
7–0 Subordinate
Bus Number
Highest bus number that is on the downstream interface.