Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-27
14.4.3 Type 1 PCI-Compatible Configuration Header Registers
The type 1 header is shown in Figure 14-22.
Section 14.4.1, “Common PCI Express-Compatible Configuration Header Registers,” describes the
registers in the first 16 bytes of the header. This section describes the registers that are unique to the type
1 header beginning at offset 0x010.
14.4.3.1 PCI Express Primary Bus Number Register (RC Mode Only)
The primary bus number register is shown in Figure 14-23.
Table 14-22 describes the primary bus number register fields.
Reserved
Address
Offset (Hex)
Device ID Vendor ID 00
Status Command 04
Class Code Revision ID 08
BIST Header Type Latency Timer Cache Line Size 0C
10
14
Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number 18
Secondary Status I/O Limit I/O Base 1C
Memory Limit Memory Base 20
Prefetchable Memory Limit Prefetchable Memory Base 24
Prefetchable Base Upper 32 Bits 28
Prefetchable Limit Upper 32 Bits 2C
I/O Limit Upper 16 Bits I/O Base Upper 16 Bits 30
Capabilities Pointer 34
Expansion ROM Base Address 38
Bridge Control Interrupt Pin Interrupt Line 3C
Figure 14-22. PCI Express PCI Express-Compatible Configuration Header—Type 1
Offset 0x018 Access: Read/Write
7 0
R
Primary Bus Number
W
Reset All zeros
Figure 14-23. PCI Express Primary Bus Number Register
Table 14-22. PCI Express Primary Bus Number Register Fields Description
Bits Name Description
7–0 Primary
Bus Number
Bus that is connected to the upstream interface. Note that this register is programmed during system
enumeration; in RC mode this register should remain 0x00.