Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-25
14.4.2.4 PCI Express Capabilities Pointer Register
The PCI Express capabilities pointer register, shown in Figure 14-18, identifies additional functionality
supported by the device.
Table 14-18 describes the PCI Express capabilities pointer.
14.4.2.5 PCI Express Interrupt Line Register (EP-Mode Only)
The PCI Express interrupt line register, shown in Figure 14-19, is used by device drivers and OS software
to communicate interrupt line routing information. Values in this register are programmed by system
software and are system-specific.
Table 14-19 describes the PCI Express interrupt line register.
Offset 0x034 Access: Read-only
7 0
R Capabilities Pointer
W
Reset01000100
Figure 14-18. PCI Express Capabilities Pointer Register
Table 14-18. PCI Express Capabilities Pointer Register Fields Description
Bits Name Description
7–0 Capabilities
Pointer
The capabilities pointer provides the offset (0x44) for additional PCI Express-compatible registers above
the common 64-byte header. Refer to Section 14.4.4, “PCI Express-Compatible Device-Specific
Configuration Space Registers.”
Offset 0x03C (EP mode only) Access: Read/Write
7 0
R
Interrupt Line
W
Reset All zeros
Figure 14-19. PCI Express Interrupt Line Register
Table 14-19. PCI Express Interrupt Line Register Fields Description
Bits Name Description
7–0 Interrupt Line Communicates interrupt line routing information.