Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-22 Freescale Semiconductor
attributes are programmed by an indirect registers access, using the PCI Express BAR Configuration
Registers. For further details see Section 14.4.7, “PCI Express BAR Configuration Registers (EP Mode).”
NOTE
To access the device internal memory-mapped configuration registers space
from the PCI Express side, the IMMRBAR address should be programmed
to one of the PCI Express EP inbound window translation address registers
(PEX_EPIWTARn) corresponding to one of the base address registers
described in this section.
14.4.2.1.1 Base Address Registers 0 and 1 (BAR0/BAR1)
BAR0 and BAR1, shown in Figure 14-13, defines the inbound memory windows in the 32-bit memory
space.
Table 14-13 describes the BAR0/BAR1 fields.
Offset 0x010 (EP mode only)
0x014 (EP mode only)
Access: Mixed
31 12 11 4 3 2 1 0
R
ADDRESS —
PREF TYPE MemSp
W
Reset0000000000000000000000000000 1 0 0 0
Figure 14-13. 32-Bit Base Address Registers (BAR0/BAR1)
Table 14-13. BAR0 and BAR1 Register Fields Description
Bits Name Description
31–12 ADDRESS Indicates the base address where the inbound memory window begins. The number of upper bits that
the device allows to be writable is selected through the PCI Express BAR configuration registers (EP
mode).
11–4 — Reserved. The device allows a 4 Kbyte window minimum.
3 PREF Prefetchable. This bit is determined by PCI Express BAR prefetch configuration register
(PEX_BAR_PF).
2–1 TYPE Type.
00 Locate anywhere in 32-bit address space.
0 MemSp Memory space indicator.