Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-21
14.4.1.10 PCI Express BIST Register
The BIST register is optional and reserved on the PCI Express controller.
14.4.2 Type 0 PCI Express-Compatible Configuration Header Registers
The type 0 header is shown in Figure 14-12.
Section 14.4.1, “Common PCI Express-Compatible Configuration Header Registers,” describes the
registers in the first 16 bytes of the header. This section describes the registers that are unique to the type
0 header beginning at offset 0x010.
14.4.2.1 PCI Express Base Address Registers (EP Mode Only)
The PCI Express base address registers (BARs) point to the beginning of distinct address ranges which the
device should claim. The device supports two 32-bit memory space BARs and two 64-bit memory space
BARs. These registers in the header configuration space are used for inbound PCI Express transactions, in
EP mode only. Note that in RC mode, the device only supports BARs defined by the inbound ATMUs.
For a standard enumeration sequence, the base address registers (BARs) registers are accessed by the Root
Complex device to determine the EP attributes. The EP local host should initialize these attributes (if
different than the default values) before accepting configuration accesses. This BAR’s size and prefetch
Reserved
Address
Offset (Hex)
Device ID Vendor ID 00
Status Command 04
Class Code Revision ID 08
BIST Header Type Latency Timer Cache Line Size 0C
Base Address Registers
10
14
18
1C
20
24
28
Subsystem ID Subsystem Vendor ID 2C
30
Capabilities Pointer 34
Expansion ROM Base Address 38
MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3C
Figure 14-12. PCI Express PCI Express-Compatible Configuration Header—Type 0