Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-20 Freescale Semiconductor
Table 14-11 describes the PCI Express latency timer register (PLTR).
14.4.1.9 PCI Express Header Type Register
The PCI Express header type register, shown in Figure 14-11, identifies the layout of the
PCI Express-compatible header.
Table 14-12 describes the PCI Express header type register.
Table 14-11. PCI Express Latency Timer Register Fields Description
Bits Name Description
7–0 Latency Timer Note that for PCI Express operation this register is ignored.
Offset 0x00E Access: Read-only
76 0
R Multifunction Header Layout
W
Reset 0x00 (EP mode)
0x01 (RC mode)
Figure 14-11. PCI Express Header Type Register
Table 14-12. PCI Express Header Type Register Fields Description
Bits Name Description
7 Multifunction Identifies whether a device supports multiple functions
0 Single-function device
1 Multiple-function device
6–0 Header Layout 0x00 Endpoint. See Figure 14-12 for type 0 layout.
0x01 Root Complex. See Figure 14-22 for type 1 layout.
All other encodings are reserved.