Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-18 Freescale Semiconductor
14.4.1.5 PCI Express Revision ID Register
The revision ID register, shown in Figure 14-7, identifies the revision of the device.
. Table 14-8 describes the revision ID register fields.
14.4.1.6 PCI Express Class Code Register
The PCI Express class code register, shown in Figure 14-8, is composed of three single-byte fields—base
class (offset 0x00B), subclass (offset 0x00A), and programming interface (offset 0x009)—that indicate the
basic functionality.
Offset 0x008 Access: Read-only
7 0
R Revision ID
W
Reset Revision specific
Figure 14-7. PCI Express Revision ID Register
Table 14-8. PCI Express Revision ID Register Fields Description
Bits Name Description
7–0 Revision ID Revision specific.
The value is 0x10.
Offset 0x009 Access: Mixed
23 16
R Base Class
W
Reset00001011
15 8
R Sub-Class
W
Reset00100000
7 0
R Programming Interface
W
Reset 0x00 RC mode
0x00 EP mode
Figure 14-8. PCI Express Class Code Register