Information
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-17
14.4.1.4 PCI Express Status Register
The status register, shown in Figure 14-6, records status information for PCI Express events.
Table 14-7 describes the PCI Express status register bits.
Offset 0x006 Access: Mixed
15 14 13 12 11 10 9 8
R Detected
parity error
Signaled
system error
Received
master-abort
Received
target-abort
Signaled
target-abort
—
Master data
parity error
W w1c w1c w1c w1c w1c
w1c
Reset All zeros
76543 0
R
———
Capabilities
list
—
W
Reset00010000
Figure 14-6. PCI Express Status Register
Table 14-7. PCI Express Status Register Fields Description
Bits Name Description
15 Detected parity
error
1
1
The error control and status bits in the command and status registers control PCI Express-compatible error reporting. PCI
Express advanced error reporting is controlled by the PCI Express device control register described in Section 14.4.4.10, “PCI
Express Device Control Register,” and the advance error reporting capability structure described in Section 14.4.5.1, “PCI
Express Advanced Error Reporting Capability ID Register,” through Section 14.4.5.11, “PCI Express Error Source
Identification Register.”
Set when a device receives a poisoned TLP regardless of the state of bit 6 in the command
register.
14 Signaled system
error
1
Set when a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit
in the command register is set.
13 Received
master-abort
1
Set when a requestor receives a completion with unsupported request completion status.
12 Received
target-abort
1
Set when a device receives a completion with completer abort completion status.
11 Signaled
target-abort
1
Set when a device completes a request using completer abort completion status.
10–9 — Reserved
8 Master data parity
error detected
1
Set by the requestor (primary side for Type1 headers) when either the requestor receives a
completion marked poisoned or the requestor poisons a write request. Note that the parity error
enable bit (bit 6) in the command register must be set before this bit can be set.
7–5 — Reserved.
4 Capabilities List All PCI Express devices are required to implement the PCI Express capability structure.
3–0 — Reserved.