Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-16 Freescale Semiconductor
the PCI Express device control register described in Section 14.4.4.10, “PCI Express Device Control
Register,” and the advance error reporting capability structure described in Section 14.4.5.1, “PCI Express
Advanced Error Reporting Capability ID Register,” through Section 14.4.5.11, “PCI Express Error Source
Identification Register.”
Table 14-6 describes the bits of the command register.
Offset 0x004 Access: Mixed
15 98765 32 1 0
R—
SERR
—
Parity error
response
—
Bus master
Memory
space
I/O space
W
Reset All zeros
Figure 14-5. PCI Express Command Register
Table 14-6. PCI Express Command Register Fields Description
Bits Name Description
15–9 — Reserved
8 SERR Controls the reporting of fatal and non-fatal errors detected by the device to the root complex.
0 Disables reporting
1 Enables reporting
7—Reserved
6 Parity error
response
Controls whether this PCI Express controller responds to parity errors.
0 Parity errors are ignored and normal operation continues.
1 Parity errors cause the appropriate bit in the PCI Express status register to be set. However, note that
errors are reported based on the values set in the PCI Express error enable and detection registers.
5–3 — Reserved
2 Bus master Enables/disables this PCI Express device to behave as a PCI Express bus master.
0 Disables the ability to generate PCI Express accesses.
1 Enables this PCI Express controller to behave as a bus master.
Clearing this bit prevent the device from issuing any memory or I/O transactions. Because MSI interrupts
are effectively memory writes, clearing this bit also disables the ability of the device to issue MSI interrupts.
1 Memory
space
Controls whether this PCI Express device (as a target) responds to memory accesses.
0 Device does not respond to PCI Express memory space accesses.
1 Device responds to PCI Express memory space accesses.
Clearing this bit prevents the device from accepting any memory transaction. It does not affect outbound
memory transactions.
0 I/O space I/O space. This bit is hardwired to 0.