Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-14 Freescale Semiconductor
14.4 PCI Express Core Configuration Header Registers
The PCI Express core implements a standard type 0/type 1 configuration space, which consists of a 64-byte
type 0 configuration space header and capability structures listed in the PCI Express specification.
The various capabilities supported are as follows:
• Power management (PM)
• PCI Express (PCI_EX)
• Message signaled interrupt (MSI) (not present for RC)
• Vital product data (VPD) (not present for RC)
• Subsystem ID and subsystem vendor ID (SSID/SSVID) (optional capability only for type-1 header
devices)
The supported PCI Express extended capabilities are as follows:
• Advanced error reporting
• Device serial number
• Power budgeting VC capability (including VC arbitration table for WRR-32/port arbitration table)
• Vendor specific capability (VSEC)
14.4.1 Common PCI Express-Compatible Configuration Header Registers
The first 64 bytes of the 256-byte PCI Express-compatible configuration space consists of a predefined
header that every PCI Express-compatible device must support. The first 16 bytes of the predefined header
are defined the same way for all PCI Express devices. These common registers are shown in Figure 14-2.
They are common to both type 0 and type 1 configuration headers.
The remaining 48 bytes of the header may have differing layouts depending on the function of the device.
Two header types apply to PCI Express. Type 0 headers, described in Section 14.4.2, “Type 0 PCI
Express-Compatible Configuration Header Registers,” are typically used by endpoints; Type 1 headers
described in Section 14.4.3, “Type 1 PCI-Compatible Configuration Header Registers,” are used by root
complexes and switches/bridges.
1
MPC8308 does not support these registers in accordance with the PCIe specification. For more information, see PCI Express
Base Specification, March 28, 2005 (Page 357-358). These registers are mentioned here only for completeness. It is
recommended not to change the reset values of these registers.
Reserved
Address
Offset (Hex)
Device ID Vendor ID 00
Status Command 04
Class Code Revision ID 08
BIST Header Type Latency Timer Cache Line Size 0C
Figure 14-2. PCI Express PCI Express-Compatible Configuration Header Common Registers