Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-9
0x110 PCI Express Correctable Error Status Register w1c 0x0000_0000 14.4.5.5/14-56
0x114 PCI Express Correctable Error Mask Register R/W 0x0000_0000 14.4.5.6/14-57
0x118 PCI Express Advanced Error Capabilities and Control Register R/W 0x0000_00A0 14.4.5.7/14-58
0x11C PCI Express Header Log Register R 0x0000_0000 14.4.5.8/14-58
0x120 PCI Express Header Log Register R 0x0000_0000
0x124 PCI Express Header Log Register R 0x0000_0000
0x128 PCI Express Header Log Register R 0x0000_0000
0x12C PCI Express Root Error Command Register R/W 0x0000_0000 14.4.5.9/14-60
0x130 PCI Express Root Error Status Register Mixed 0x0000_0000 14.4.5.10/14-60
0x134 PCI Express Error Source Identification Register R 0x0000_0000 14.4.5.11/14-61
PCI Express Core Control and Status Registers (CSRs)
0x404 PCI Express LTSSM State Status Register (PEX_LTSSM_STAT) R 0x0000_0000 14.4.6.1/14-62
0x41C PCI Express N_FTS Control Register (PEX_NFTS_CTRL) R/W 0x0000_4040 14.4.6.2/14-63
0x438 PCI Express ACK Replay Timeout Register
(PEX_ACKRPLY_TO)
R/W 0x005B_2090 14.4.6.3/14-64
0x440 PCI Express Core Clock Ratio Register (PEX_GCLK_RATIO) Mixed 0x0000_0010 14.4.6.4/14-65
0x450 PCI Express Power Management Timer Register
(PEX_PM_TIMER)
Mixed 0x000A_63E4 14.4.6.5/14-66
0x454 PCI Express PME Time-Out Register (PEX_PME_TIMEOUT) Mixed 0x00FD_4BC0 14.4.6.6/14-67
0x45C PCI Express ASPM Request Timer Register
(PEX_ASPM_REQTMR) (RC mode only)
R/W 0x0000_0629 14.4.6.7/14-67
0x478 PCI Express Subsystem Vendor ID Update Register
(PEX_SSVID_UPDATE)
R/W 0x0000_0000 14.4.6.8/14-68
0x47C PCI Express Device Capabilities Update Register
(PEX_DEVCAP_UPDATE)
R/W 0x0000_0000 14.4.6.9/14-68
0x480 PCI Express Link Capabilities Update Register
(PEX_LINKCAP_UPDATE)
R/W 0x0000_3D41 14.4.6.10/14-69
0x490 PCI Express Slot Capabilities Update Register
(PEX_SLCAP_UPDATE)
R/W 0x0000_07C0 14.4.6.11/14-71
0x4B0 PCI Express Configuration Ready Register (PEX_CFG_READY) Mixed 0x0000_0000 14.4.6.12/14-71
PCI Express BAR Configuration Registers (EP Mode)
0x4D8 PCI Express BAR Size Low Configuration Register
(PEX_BAR_SIZEL)
R/W 0xFC00_0000 14.4.7.1/14-72
0x4DC Reserved — — —
0x4E0 PCI Express BAR Select Configuration Register
(PEX_BAR_SEL)
R/W 0x0000_0400 14.4.7.2/14-73
Table 14-3. PCI Express Memory Map (continued)
Offset Register Access Reset Section/Page
PCI Express—Block Base Address 0x0_9000