Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-5
14.1.4.3 Reference Clock
The reference clock for the PCI Express PHY is set to 100 MHz upon POR. To change the reference clock
frequency after POR, program the SRDSCR4 (see Section 15.3.5, “SerDes Control Register 4
(SRDSCR4)”) and initiate a SerDes PHY reset sequence.
By default, PCI Express controller clock is the same as CSB clock.
14.2 External Signal Descriptions
PCI Express defines the connection between two devices as a link, which can be composed of a single lane
or multiple lanes. Each lane consists of a differential pair for transmitting (TXn and TXn) and a differential
pair for receiving (RXn and RXn) with an embedded data clock.
Table 14-1 describes the external PCI Express interface signals.
14.3 Memory Map/Register Definitions
The PCI Express interface supports the following register types:
• Memory-mapped registers—Control PCI Express address translation, PCI Express error
management, and PCI Express configuration register access on the device. These registers are
described in Section 14.3.1, “PCI Express Memory Map.”
• PCI Express configuration registers within the PCI Express configuration header—Specified by
the PCI Express specification for every PCI Express device. They are described in Section 14.4.1,
“Common PCI Express-Compatible Configuration Header Registers.”
From the PCI Express side, the configuration header registers can be accessed through configuration
access, and the memory-mapped registers can be accessed through memory transactions after the inbound
translation window is programmed. From the CSB side, all these registers are memory-mapped.
14.3.1 PCI Express Memory Map
The PCI Express memory-mapped registers, listed in Table 14-3, are accessed by reading and writing to
an address composed of the base address (specified in the IMMRBAR on the CSB side or the ATMU
windows on the PCI Express side) plus the offset of the specific register to be accessed. In this table and
in the register figures and fields description, the following access definitions apply:
• Reserved fields are always ignored for the purposes of determining access type.
• R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
• w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Table 14-1. PCI Express Interface Signals—Detailed Signal Descriptions
Signal I/O Description
RXA/RXA I Receive data. Receive data differential signal pair carry PCI Express packet information.
TXA/TXA O Transmit data. The transmit data differential signal pair carry PCI Express packet information.