Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-4 Freescale Semiconductor
14.1.3 Features
The following is a list of PCI Express controller features:
• Designed to be compatible with the PCI Express Base Specification, Version 1.0a
• Root complex (RC) and endpoint (EP) configurations
• 32- and 64-bit address support
• PCI Express link of 1 lane
• Access to all PCI Express memory
• Access to I/O address spaces as requestor only in RC mode
• Posting of processor-to-PCI Express and PCI Express-to-memory writes
• Strong and relaxed transaction ordering rules
• PCI Express configuration registers
• Baseline and advanced error reporting
• One virtual channel (VC0)
• 128-byte maximum payload size (Max_Payload_Size) for memory read and write operations
• Four inbound general-purpose translation windows
• Four outbound translation windows
• Up to four outstanding PCI Express transactions from each controller (posted or non-posted)
• Credit-based flow control management
• PCI Express messages and interrupts
• Maximum 32-byte payload transactions from the CSB
• Interrupt generation from messages or upon detection of errors
• Read and Write DMA engines
• Support polarity inversion
14.1.4 Modes of Operation
This section describes how some parameters that affect the PCI Express controller operating modes are
determined by dedicated memory mapped registers.
14.1.4.1 Root Complex/Endpoint Modes
The PCI Express controller can function as either a root complex (RC) or an endpoint (EP) device. The
PCI Express control registers 1 and 2 determine the RC/EP mode; see Section 5.2.2.11, “PCI Express
Control Registers (PECR1).”
14.1.4.2 Link Width
The link width of the PCI Express controller is 1.