Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-3
As an initiator, the device supports memory read and write operations with a maximum payload of
128 bytes and I/O transactions. In addition, outbound configurations are supported if the device is in RC
mode. As a target interface, the device accepts read and write operations to local memory space.
Furthermore, as an EP device, the device accepts configuration transactions to the internal PCI Express
configuration registers. Inbound I/O transactions are not supported.
14.1.1 MPC8308 as a PCI Express Initiator
Outbound CSB transactions to PCI Express are first mapped to a translation window to determine which
PCI Express transactions are to be issued. A transaction from the CSB can become a memory, I/O, or
configuration transaction on the PCI Express bus depending on the window attributes. A transaction can
be broken up into smaller transactions depending on the original request size, transaction type, PCI
Express device control register’s Max_Payload_Size field (for writes) and PCI Express device control
register’s Max_Read_Request_Size field (for reads). The device performs PCI Express ordering rule
checks to determine the next transaction to be sent on the PCI Express bus. In general, transactions are
serviced in the order they are received from the CSB. The device allows reordering of higher-priority
transactions to bypass lower-priority transactions only when there is a stall condition. For posted write
transactions, after all data is received on the CSB, the data is forwarded to the PCI Express bus and the
transaction is considered to be complete. For non-posted write transactions, the device waits for a
completion to return from the link partner before considering the transaction to be complete. For
non-posted read transactions, the device waits for all completion packets to return from the link partner
and then forwards all data back to the CSB before terminating the transaction.
There are two methods of generating PCI Express outbound transactions:
• One of the CSB masters, such as the e300 host, directly initiates a transaction. This is referred to
as “PIO.”
• The write or read DMA engines, which are part of the PCI Express controller CSB bridge, is used.
The DMA method is more efficient for transferring large chunks of data. The outbound widows are used
and shared by both methods.
14.1.2 MPC8308 as a PCI Express Target
Inbound PCI Express transactions to the CSB are first mapped to the CSB address space through a
translation window. A transaction can be broken up into smaller transactions when it is sent to the CSB
depending on the original size, byte enables, and starting/ending addresses. The device performs PCI
Express ordering rule checks to determine the next transaction to be sent to the CSB. In general,
transactions are serviced in the order they are received from the PCI Express bus. The device allows
reordering of higher-priority transactions to bypass lower-priority transactions only when there is a stall
condition. For posted write transactions, after all data is received on the PCI Express bus, the data is
forwarded to the CSB and the transaction is considered to be complete. For non-posted read transactions,
the device waits for enough completion packets (dependent on the packet length) to return and then
forwards data back to the PCI Express bus. This process continues until there are no more completion
packets left to be sent.