Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-2 Freescale Semiconductor
Figure 14-1 is a high-level block diagram of the PCI Express controller.
Figure 14-1. PCI Express Controller Block Diagram
The PCI Express controller connects the coherent system bus (CSB) to the PCI Express bus, which is a
2.5-GHz serial interface that supports 1 lane. As both a master (initiator) and a target device, the
PCI Express interface is capable of high bandwidth data transfer and is designed to support the next
generation of I/O devices. When it comes out of reset, the PCI Express interface performs link width
negotiation and exchanges flow control credits with its link partner. When link auto-negotiation finishes,
the controller is ready for operation.
Internally, the design contains queues to keep track of inbound and outbound transactions. The control
logic handles buffer management, bus protocol, transaction spawning, and tag generation. In addition,
memory blocks store inbound and outbound data.
The device can be configured to operate in either root complex (RC) or endpoint (EP) mode. An RC device
connects the CPU/memory subsystem to the I/O devices, while an EP device typically denotes a peripheral
or I/O device. In RC mode, a type 1 configuration header is used. In EP mode, a type 0 configuration
header is used.
CSB Interface
Message Manager
TXRX Transaction Layer
Configuration
Registers
TXRX Data Link Layer
TXRX MAC Layer
SerDes Interface
PCI Express Link
CSB Bridge
PCI Express Core Interface
PCI Express Core
RDMA
WDMA
Configuration
Registers
SerDes
Configuration
Registers