Information
Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
1-10 Freescale Semiconductor
1.2.2 DDR2 Memory Controller
This fully programmable DDR2 SDRAM controller supports most JEDEC standard 8 or 16 DDR2
memories available today, including buffered and unbuffered DIMMs. However, mixing non registered
and registered DIMMs in the same system is not supported.
The DDR memory controller includes the following features:
• Support for DDR2 SDRAM
• 16- or 32-bit SDRAM data bus
• Programmable settings for meeting all SDRAM timing parameters
• Many different SDRAM configurations supported
— Support for two physical banks (chip selects)
— Support for 64-Mbit to 1-Gbit devices with 8/16 data ports. Some 2-Gbit devices are
supported depending on the internal device configuration.
— Support for unbuffered and registered DIMMs
• Support for data mask signals and read-modify-write operations for sub-double word writes
• Four-entry input request queue
• Open page management (dedicated entry for each sub-bank)
1.2.3 Dual Enhanced Three-Speed Ethernet Controllers
The MPC8308 has two on-chip enhanced three-speed Ethernet controllers. The eTSECs incorporate a
media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps Ethernet/IEEE Std.
802.3 networks with MII and RGMII physical interfaces. The eTSECs include 2-Kbyte receive and
10-Kbyte transmit FIFOs and DMA functions. They also support IEEE Std. 1588.
The buffer descriptors are based on the MPC8260 and MPC860T 10/100 Ethernet programming models.
Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with
minimal change.
The MPC8308 eTSECs support programmable CRC generation and checking, RMON statistics, and
jumbo frames of up to 9.6 Kbytes.
Each eTSEC provides hardware support for accelerating TCP/IP packet transmission and reception. By
default, TCP/IP acceleration is not enabled, and the eTSEC processes frames as pure Ethernet frames.
TCP/IP acceleration can be performed at a number of levels. The eTSEC can parse frames at layer 2 of the
stack only (Ethernet headers and switching headers), layers 2 to 3 (including IP v4 or IP v6), or layers 2
to 4 (including TCP and UDP).
On receive, the eTSEC provides protocol header recognition, header verification (IP v4 header checksum
verification), and TCP/UDP payload checksum verification including verification of associated
pseudo-header checksums. On transmit, the eTSEC provides IP v4 and TCP/UDP header checksum
generation. The eTSEC does not checksum transmitted packets with IP header options or IP fragments.