Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-1
Chapter 14
PCI Express Interface Controller
The MPC8308 PCI Express interface is compatible with the PCI Express™ Base Specification, Revision
1.0a (available from http://www.pcisig.org). It is beyond the scope of this manual to document the
intricacies of the PCI Express protocol. This chapter describes the PCI Express controller of this device
and provides a basic description of the PCI Express protocol. The specific emphasis is directed at how the
device implements the PCI Express specification. Designers of systems incorporating PCI Express devices
should refer to the specification for a thorough description of PCI Express.
NOTE
• Much of the available PCI Express literature refers to a 16-bit quantity
as a WORD and a 32-bit quantity as a DWORD. This is inconsistent
with the terminology in the rest of this manual where the terms ‘word’
and ‘double word’ refer to a 32-bit and 64-bit quantity, respectively.
Where necessary to avoid confusion, the precise number of bits or bytes
is specified.
• The PCI Express engine does not support misaligned byte transfers. It
must be DWORD aligned to the CSB bus.
14.1 Introduction
The PCI Express controller is a mechanism for communicating with PCI Express devices. The controller
contains three major parts:
• PCI Express core—Handles the transaction, data link and MAC layers and contains the
configuration header and control registers.
• CSB bridge—Controls the transfer of the transactions between the PCI Express transaction layer
and the CSB, and include Write and Read DMA engines, a message manager and a set of
configuration registers.
• SerDes—Controls the transfer between the PCI Express MAC layer and the physical link, and
includes another set of configuration registers (described in Chapter 15, “SerDes PHY”).