Information

Universal Serial Bus Interface

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

13-156 Freescale Semiconductor

13.10 Timing Diagrams

This section contains diagrams showing the basic operation of the ULPI interface. For a more detailed

description refer to the ULPI Specifications.

Figure 13-66 shows ULPI timing.

Figure 13-66. ULPI Timing

Table 13-98 summarizes the ULPI timing parameters.

Table 13-98. ULPI Timing

Parameter Symbol Min Max Units

Control signal setup time TSC — 4 ns

Data setup time TSD — 4 ns

Control signal hold time THC 0 — ns

Data hold time THD 0 — ns

Control output delay TDC 2 7 ns

Data output delay TDD 2 7 ns

PHY_CLK

DIR/NXT

DATA (from PHY)

STP

DATA (to PHY)