Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-154 Freescale Semiconductor
13.9.3 Non-Zero Fields the Register File
Some of the reserved fields and reserved addresses in the capability registers and operational registers have
use in device mode, the following must be adhered to:
• Write operations to all EHCI reserved fields (some of which are device fields in the DR module)
in the operation registers should always be written to zero. This is an EHCI requirement of the
device controller driver that must be adhered to.
• Read operations by the module must properly mask EHCI reserved fields (some of which are
device fields in the DR module registers).
13.9.4 SOF Interrupt
The SOF interrupt is a free running 125 µsec interrupt for host mode. EHCI does not specify this interrupt,
but it has been added for convenience and as a potential software time base. Note that the free running
interrupt is shared with the device-mode start-of-frame interrupt. See Section 13.3.2.2, “USB Status
Register (USBSTS),” and Section 13.3.2.3, “USB Interrupt Enable Register (USBINTR),” for more
information.
13.9.5 Embedded Design
This is an Embedded USB Host Controller as defined by the EHCI specification and thus does not
implement the PCI configuration registers.
13.9.5.1 Frame Adjust Register
Given that the optional PCI configuration registers are not included in this implementation, there is no
corresponding bit level timing adjustments like those provided by the Frame Adjust register in the PCI
configuration registers. Starts of microframes are timed precisely to 125 µsec using the transceiver clock
as a reference clock. That is, 60 MHz transceiver clock for 8-bit physical interfaces and full-speed serial
interfaces or 30 MHz transceiver clock for 16-bit physical interfaces.
13.9.6 Miscellaneous Variations from EHCI
The modules support multiple physical interfaces which can operate in different modes when the module
is configured with the software programmable Physical Interface Modes. The control bits for selecting the
PHY operating mode have been added to the PORTSC register providing a capability that is not defined
by the EHCI specification.
13.9.6.1 Discovery
This section discusses port reset and port speed detection.
13.9.6.1.1 Port Reset
The port connect methods specified by EHCI require setting the port reset bit in the register for a duration
of 10 msec. Due to the complexity required to support the attachment of devices that are not high speed