Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-153
13.9.1.5.3 Asynchronous Transaction Scheduling and Buffer Management
The following Universal Serial Bus Revision 2.0 Specification items are implemented in the embedded
transaction translator:
• USB 2.0–11.17.3
— Sequencing is provided and a packet length estimator ensures no full-speed/low-speed packet
babbles into SOF time.
• USB 2.0–11.17.4
— Transaction tracking for 2 data pipes.
• USB 2.0–11.17.5
— Clear_TT_Buffer capability provided
13.9.1.5.4 Periodic Transaction Scheduling and Buffer Management
The following Universal Serial Bus Revision 2.0 Specification items are implemented in the embedded
transaction translator:
• USB 2.0–11.18.6.[1-2]
— Abort of pending start-splits
– EOF (and not started in microframes 6)
– Idle for more than 4 microframes
— Abort of pending complete-splits
–EOF
– Idle for more than 4 microframes
NOTE
There is no data schedule mechanism for these transactions other than the
microframe pipeline. The embedded TT assumes the number of packets
scheduled in a frame does not exceed the frame duration (1 msec) or else
undefined behavior may result.
13.9.1.5.5 Multiple Transaction Translators
The maximum number of embedded transaction translators that is currently supported is one as indicated
by the N_TT field in the HCSPARAMS register. See Section 13.3.1.3, “Host Controller Structural
Parameters (HCSPARAMS),” for more information.
13.9.2 Device Operation
The co-existence of a device operational controller within the DR module has little effect on EHCI
compatibility for host operation except as noted in this section.