Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-152 Freescale Semiconductor
bus between EHCI host controller driver and the USB FS/LS bus. These sections will briefly discuss the
operational model for how the EHCI and transaction translator operational models are combined without
the physical bus between. The following sections assume the reader is familiar with both the EHCI and
USB 2.0 transaction translator operational models.
13.9.1.5.1 Microframe Pipeline
The EHCI operational model uses the concept of H-frames and B-frames to describe the pipeline between
the Host (H) and the Bus (B). The embedded transaction translator shall use the same pipeline algorithms
specified in the Universal Serial Bus Revision 2.0 Specification for a Hub-based transaction translator.
All periodic transfers always begin at B-frame 0 (after SOF) and continue until the stored periodic transfers
are complete. As an example of the microframe pipeline implemented in the embedded transaction
translator, all periodic transfers that are tagged in EHCI to execute in H-frame 0 will be ready to execute
on the bus in B-frame 0.
It is important to note that when programming the S-mask and C-masks in the EHCI data structures to
schedule periodic transfers for the embedded transaction translator, the EHCI host controller driver must
follow the same rules specified in EHCI for programming the S-mask and C-mask for downstream
Hub-based transaction translators.
Once periodic transfers are exhausted, any stored asynchronous transfer are moved. Asynchronous
transfers are opportunistic in that they shall execute whenever possible and their operation is not tied to
H-frame and B-frame boundaries with the exception that an asynchronous transfer cannot babble through
the SOF (start of B-frame 0).
13.9.1.5.2 Split State Machines
The start and complete split operational model differs from EHCI slightly because there is no bus medium
between the EHCI controller and the embedded transaction translator. Where a start or complete-split
operation would occur by requesting the split to the HS hub, the start/complete split operation is simple an
internal operation to the embedded transaction translator. Table 13-97 summarizes the conditions where
handshakes are emulated from internal state instead of actual handshakes to HS split bus traffic.
Table 13-97. Emulated Handshakes
Condition Emulate TT Response
Start-Split: All asynchronous buffers full NAK
Start-Split: All periodic buffers full ERR
Start-Split: Success for start of Async. Transaction ACK
Start-Split: Start Periodic Transaction No Handshake (Ok)
Complete-Split: Failed to find transaction in queue Bus Time Out
Complete-Split: Transaction in Queue is Busy NYET
Complete-Split: Transaction in Queue is Complete [Actual Handshake from FS/LS device]