Information

Overview

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 1-9

Figure 1-2 provides a block diagram of the e300 core that shows how the execution units (IU1, IU2, FPU,

BPU, LSU, and SRU) operate independently and in parallel. Note that this is a conceptual diagram that

does not attempt to show how these features are physically implemented on the chip.

Figure 1-2. MPC8308 Integrated e300c3 Core Block Diagram

64-Bit

32-Bit

Branch

Processing

Unit

64-Bit Data Bus

32-Bit Address Bus

Instruction Unit

Integer

Units (2)

Floating-

Point Unit

FPR File

FP Rename

Registers

16-Kbyte

D Cache