Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-149
13.8.6.2 Low-Frequency Interrupts
The low frequency events include the interrupts shown in Table 13-94. These interrupts can be handled in
any order because they do not occur often in comparison to the high-frequency interrupts.
13.8.6.3 Error Interrupts
Error interrupts are the least frequently occurring events. They should be placed last in the interrupt service
routine. Table 13-95 shows the error interrupt events.
13.9 Deviations from the EHCI Specifications
The host mode operation of the USB DR module is nearly EHCI-compatible with few minor differences.
For the most part, the module conforms to the data structures and operations described in Section 3, “Data
Structures,” and Section 4, “Operational Model,” in the EHCI specification. The particulars of the
deviations occur in the following areas:
• Embedded transaction translator—Allows direct attachment of FS and LS devices in host mode
without the need for a companion controller.
1b USB Interrupt
ENDPTCOMPLETE
Handle completion of dTD as indicated in Section 13.8.4, “Managing Queue Heads”.
2 SOF Interrupt Action as deemed necessary by application. This interrupt may not have a use in all
applications.
1
It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during the Interrupt Service
Routine.
Table 13-94. Low Frequency Interrupt Events
Interrupt Action
Port Change Change software state information.
Sleep Enable (Suspend) Change software state information. Low power handling as necessary.
Reset Received Change software state information. Abort pending transfers.
Table 13-95. Error Interrupt Events
Interrupt Action
USB Error Interrupt This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD
will more aptly handle packet-level errors by checking dTD status field upon receipt of USB Interrupt
(w/ ENDPTCOMPLETE).
System Error Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD.
Table 13-93. Interrupt Handling Order (continued)
Execution
Order
Interrupt Action