Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-143
must write the prime bit. The USB_DR will prime the isochronous endpoint in (micro)frame N – 1 so that
the device controller will execute delivery during (micro)frame N.
CAUTION
Priming an endpoint towards the end of (micro)frame N – 1 will not
guarantee delivery in (micro)frame N. The delivery may actually occur in
(micro)frame N + 1 if device controller does not have enough time to
complete the prime before the SOF for packet N is received.
13.8.3.6.2 Isochronous Endpoint Bus Response Matrix
Table 13-90 shows the isochronous endpoint bus response matrix.
13.8.4 Managing Queue Heads
Figure 13-64 shows the endpoint queue head diagram.
Figure 13-64. Endpoint Queue Head Diagram
Table 13-90. Isochronous Endpoint Bus Response Matrix
Stall Not Primed Primed Underflow Overflow
Setup
STALL STALL STALL N/A N/A
In
NULL
1
Packet
1
Zero Length Packet.
NULL Packet Transmit BS Error
2
2
Force Bit Stuff Error.
N/A
Out
Ignore Ignore Receive N/A Drop Packet
Ping
Ignore Ignore Ignore Ignore Ignore
Invalid
Ignore Ignore Ignore Ignore Ignore
Transfer Buffer Pointer
Transfer
Buffer
Endpoint QH 1—Out
Endpoint QH 0—In
Endpoint QH 0—Out
Transfer
Buffer
Transfer
Buffer
Transfer
Buffer
Transfer Buffer Pointer
Endpoint Queue HeadsENDPOINTLISTADDR
Up to
Transfer
Buffer
Pointer
Transfer Buffer Pointer
Endpoint Transfer Descriptor
•
•
•
32 Elements