Information

Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
1-8 Freescale Semiconductor
interrupt routines or other important (time-sensitive) instruction sequences into the instruction cache. It
allows data to be locked into the data cache, which may be important to code that must have deterministic
execution.
The e300 core has high-performance 64-bit data bus and 32-bit address bus interfaces to the rest of the
device. The e300 core supports single-beat and burst data transfers for memory accesses and
memory-mapped I/O operations.