Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-140 Freescale Semiconductor
After priming the packet, the DCD must verify a new setup packet has not been received by reading the
ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime will complete
when the associated bit in the ENDPTPRIME register is zero and the associated bit in the ENDPTSTATUS
register is a one. If a prime fails, that is, The ENDPTPRIME bit goes to zero and the ENDPTSTATUS bit
is not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setup
arriving during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit is
cleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet.
Should a setup arrive after the data stage is primed, the device controller will automatically clear the prime
status (ENDPTSTATUS) to enforce data coherency with the setup packet.
NOTE
The MULT field in the dQH must be set to ‘00’ for bulk, interrupt, and
control endpoints.
NOTE
Error handling of data phase packets is the same as bulk packets described
previously.
13.8.3.5.3 Status Phase
Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime
the endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTAT
as described above in the data phase.
NOTE
The MULT field in the dQH must be set to ‘00’ for bulk, interrupt, and
control endpoints.
NOTE
Error handling of data phase packets is the same as bulk packets described
previously.
13.8.3.5.4 Control Endpoint Bus Response Matrix
Table 13-89 shows the device controller response to packets on a control endpoint, according to the device
controller state.
Table 13-89. Control Endpoint Bus Response Matrix
Token
Type
Endpoint State
Setup
Lockout
Stall
Not
Primed
Primed Underflow Overflow
Setup
ACK ACK ACK N/A SYSERR
1
In
STALL NAK Transmit BS Error
2
N/A N/A
Out
STALL NAK Receive +
NYET/ACK
3
N/A NAK N/A