Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-132 Freescale Semiconductor
As a result of entering the address state, the device address register (DEVICEADDR) must be programmed
by the DCD.
Entry into the configured indicates that all endpoints to be used in the operation of the device have been
properly initialized by programming the ENDPTCTRLn registers and initializing the associated queue
heads.
13.8.2.1 Bus Reset
A bus reset is used by the host to initialize downstream devices. When a bus reset is detected, the USB_DR
controller will renegotiate its attachment speed, reset the device address to 0, and notify the DCD by
interrupt (assuming the USB reset interrupt enable bit, USBINTR[URE], is set). After a reset is received,
all endpoints (except endpoint 0) are disabled and any primed transactions are canceled by the device
controller. The concept of priming is clarified below, but the DCD must perform the following tasks when
a reset is received:
1. Clear all setup token semaphores by reading the ENDPTSETUPSTAT register and writing the same
value back to the ENDPTSETUPSTAT register.
2. Clear all the endpoint complete status bits by reading the ENDPTCOMPLETE register and writing
the same value back to the ENDPTCOMPLETE register.
3. Cancel all primed status by waiting until all bits in the ENDPTPRIME are 0 and then writing
0xFFFF_FFFF to ENDPTFLUSH.
4. Read the reset bit in the PORTSC register (PORTSC[PR]) and make sure that it is still active.
— A USB reset occurs for a minimum of 3 ms, and the DCD must reach this point in the reset
cleanup before end of the reset occurs.
— If it does not, a hardware reset of the device controller is recommended. A hardware reset can
be performed by writing a one to the USB_DR reset bit in (USBCMD[RST]). Note that a
hardware reset will cause the device to detach from the bus by clearing USBCMD[RS] bit.
Thus, the DCD must completely re-initialize the USB_DR after a hardware reset.
5. Free all allocated dTDs because they will no longer be executed by the device controller. If this is
the first time the DCD is processing a USB reset event, then it is likely that no dTDs have been
allocated.
At this time, the DCD may release control back to the OS because no further changes to the device
controller are permitted until a Port Change Detect is indicated.
After a Port Change Detect, the device has reached the default state and the DCD can read the PORTSC
to determine if the device is operating in FS or HS mode. At this time, the device controller has reached
normal operating mode and DCD can begin enumeration according to the USB Chapter 9, Device
Framework.
NOTE
The device DCD may use the FS/HS mode information to determine the
bandwidth mode of the device.
In some applications, it may not be possible to enable one or more pipes while in FS mode. Beyond the
data rate issue, there is no difference in DCD operation between FS and HS modes.