Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-131
Figure 13-63. USB 2.0 Device States
States powered, attach, defaultFS/HS, suspendFS/HS are implemented in the USB_DR and are
communicated to the DCD using status bits, as shown in Table 13-83:
It is the responsibility of the DCD to maintain a state variable to differentiate between the defaultFS/HS
state and the address/configured states. Change of state from default to address and the configured states
is part of the enumeration process described in the device framework section of the USB 2.0 Specification.
Table 13-83. Device Controller State Information Bits
Bits Register
DCSuspend (SLI) USBSTS
USB Reset Received (URI) USBSTS
Port Change Detect (PCI) USBSTS
High-Speed Port PORTSC
Powered
Active State
Attach
Set Run/Stop Bit
to Run Mode
Default
FS/HS
Address
FS/HS
Configured
FS/HS
Suspend
FS/HS
Bus Inactive
Bus Activity
Suspend
FS/HS
Bus Inactive
Bus Activity
Suspend
FS/HS
Bus Inactive
Bus Activity
When the Host
Resets the Device
Returns to the
Default State
Power
Interruption
Address Assigned
Device
Reset
Configured
Device
Deconfigured
Inactive State
Software Only State