Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-130 Freescale Semiconductor
NOTE
Transitioning from host mode to device mode requires a device controller
reset before modifying USBMODE.
2. Optionally modify the BURSTSIZE register.
3. Program PORTSC[PTS] if using a non-ULPI PHY.
4. Set CONTROL[USB_EN]
5. Allocate and initialize device queue heads in system memory Minimum: Initialize device queue
heads 0 Tx and 0 Rx.
NOTE
All device queue heads must be initialized for control endpoints before the
endpoint is enabled. Device queue heads for non-control endpoints must be
initialized before the endpoint can be used.
For information on device queue heads, refer toSection 13.7, “Device Data Structures.”
6. Configure the ENDPOINTLISTADDR pointer.
For additional information on ENDPOINTLISTADDR, refer to the register table.
7. Enable the microprocessor interrupt associated with the USB DR module and optionally change
setting of USBCMD[ITC].
Recommended: enable all device interrupts including: USBINT, USBERRINT, Port Change
Detect, USB Reset Received, DCSuspend.
For a list of available interrupts refer to the USBINTR and the USBSTS register tables.
8. Set USBCMD[RS] to run mode.
After the run bit is set, a device reset will occur. The DCD must monitor the reset event and set the
DEVICEADDR register, set the ENDPTCTRLx registers, and adjust the software state as
described in Section 13.8.2.1, “Bus Reset.”
NOTE
Endpoint 0 is designed as a control endpoint only and does not need to be
configured using ENDPTCTRL0 register.
It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setup
packet. The contents of the first setup packet will require a response in accordance with USB device
framework command set.
13.8.2 Port State and Control
From a chip or system reset, the USB_DR enters the powered state. A transition from the powered state to
the attach state occurs when the run/stop bit (USBCMD[RS]) is set to a ‘1’. After receiving a reset on the
bus, the port will enter the defaultFS or defaultHS state in accordance with the protocol reset described in
Appendix C.2 of the USB Specification Rev. 2.0. Figure 13-63 depicts the state of a USB 2.0 device.