Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-127
Table 13-77 describes the multiple mode control fields.
13.7.2 Endpoint Transfer Descriptor (dTD)
The dTD describes the location and quantity of data to be sent/received for given transfer to the device
controller. The DCD should not attempt to modify any field in an active dTD except the Next Link Pointer,
which should only be modified as described in Section 13.8.5, “Managing Transfers with Transfer
Descriptors.”
Figure 13-62 shows the endpoint transfer descriptor.
Table 13-78 describes the next dTD pointer fields.
Table 13-77. Multiple Mode Control
DWord Bits Description
1 31–0 Setup Buffer 0. This buffer contains bytes 3 to 0 of an incoming setup buffer packet and is written by the device
controller to be read by software.
2 31–0 Setup Buffer 1. This buffer contains bytes 7 to 4 of an incoming setup buffer packet and is written by the device
controller to be read by software.
313029282726252423222120191817161514131211109876543210offset
Next Link Pointer 0000 T 0x00
0 Total Bytes
1
1
Device controller read/write; all others read-only.
ioc
000 MultO 00 Status
1
0x04
Buffer Pointer (Page 0) Current Offset
1
0x08
Buffer Pointer (Page 1) 0 Frame Number
1
0x0C
Buffer Pointer (Page 2) 0000_0000_0000 0x10
Buffer Pointer (Page 3) 0000_0000_0000 0x14
Buffer Pointer (Page 4) 0000_0000_0000 0x18
Figure 13-62. Endpoint Transfer Descriptor (dTD)
Table 13-78. Next dTD Pointer
Bits Description
31–5 Next transfer element pointer. This field contains the physical memory address of the next dTD to be processed. The
field corresponds to memory address signals [31:5], respectively.
4–1 Reserved, should be cleared. Bits reserved for future use and should be cleared.
0 Terminate (T). 1=pointer is invalid. 0=Pointer is valid (points to a valid Transfer Element Descriptor). This bit indicates
to the Device Controller that there are no more valid entries in the queue.