Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor vii
Figures
Figure
Number Title
Page
Number
7.4.2 Instruction Set and Addressing Modes...................................................................... 7-26
7.4.3 Cache Implementation............................................................................................... 7-29
7.4.4 Interrupt Model.......................................................................................................... 7-31
7.4.5 Memory Management................................................................................................ 7-35
7.4.6 Instruction Timing ..................................................................................................... 7-36
7.4.7 Core Interface ............................................................................................................ 7-37
7.4.8 Debug Features ......................................................................................................... 7-39
7.5 Differences Between Cores........................................................................................... 7-40
Chapter 8
Integrated Programmable Interrupt Controller (IPIC)
8.1 Introduction...................................................................................................................... 8-1
8.2 Features............................................................................................................................ 8-4
8.3 Modes of Operation ......................................................................................................... 8-4
8.3.1 Core Enable Mode ....................................................................................................... 8-4
8.3.2 Core Disable Mode...................................................................................................... 8-4
8.4 External Signal Description............................................................................................. 8-5
8.4.1 Overview...................................................................................................................... 8-5
8.4.2 Detailed Signal Descriptions ....................................................................................... 8-5
8.5 Memory Map/Register Definition ................................................................................... 8-6
8.5.1 System Global Interrupt Configuration Register (SICFR) .......................................... 8-8
8.5.2 System Global Interrupt Vector Register (SIVCR)...................................................... 8-9
8.5.3 System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L).................. 8-12
8.5.4 System Internal Interrupt Group A Priority Register (SIPRR_A)............................. 8-14
8.5.5 System Internal Interrupt Group B Priority Register (SIPRR_B) ............................. 8-15
8.5.6 System Internal Interrupt Group C Priority Register (SIPRR_C) ............................. 8-16
8.5.7 System Internal Interrupt Group D Priority Register (SIPRR_D)............................. 8-16
8.5.8 System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L) ...................... 8-17
8.5.9 System Internal Interrupt Control Register (SICNR) ................................................ 8-18
8.5.10 System External Interrupt Pending Register (SEPNR).............................................. 8-20
8.5.11 System Mixed Interrupt Group A Priority Register (SMPRR_A)............................. 8-21
8.5.12 System Mixed Interrupt Group B Priority Register (SMPRR_B)............................. 8-22
8.5.13 System External Interrupt Mask Register (SEMSR)................................................. 8-22
8.5.14 System External Interrupt Control Register (SECNR).............................................. 8-23
8.5.15 System Error Status Register (SERSR) ..................................................................... 8-25
8.5.16 System Error Mask Register (SERMR)..................................................................... 8-25
8.5.17 System Error Control Register (SERCR) .................................................................. 8-26
8.5.18 System External interrupt Polarity Control Register (SEPCR) ................................. 8-26
8.5.19 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L) ...................... 8-27
8.5.20 System External Interrupt Force Register (SEFCR).................................................. 8-29