Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-120 Freescale Semiconductor
NOTE
The only method software should use for acknowledging an interrupt is by
transitioning the appropriate status bits in the USBSTS register from a one
to a zero.
13.6.14.1 Transfer/Transaction Based Interrupts
These interrupt sources are associated with transfer and transaction progress. They are all dependent on
the next interrupt threshold.
13.6.14.1.1 Transaction Error
A transaction error is any error that caused the host controller to think that the transfer did not complete
successfully. Table 13-73 lists the events/responses that the host can observe as a result of a transaction.
The effects of the error counter and interrupt status are summarized in the following paragraphs. Most of
these errors set the XactErr status bit in the appropriate interface data structure.
There is a small set of protocol errors that relate only when executing a queue head and fit under the
umbrella of a WRONG PID error that are significant to explicitly identify. When these errors occur, the
XactErr status bit in the queue head is set and the Cerr field is decremented. When the PID Code indicates
a SETUP, the following responses are protocol errors and result in XactErr bit being set and the Cerr field
being decremented.
• EPS field indicates a high-speed device and it returns a Nak handshake to a SETUP.
• EPS field indicates a high-speed device and it returns a Nyet handshake to a SETUP.
• EPS field indicates a low- or full-speed device and the complete-split receives a Nak handshake.
13.6.14.1.2 Serial Bus Babble
When a device transmits more data on the USB than the host controller is expecting for this transaction, it
is defined to be babbling. In general, this is called a packet babble. When a device sends more data than
the maximum length number of bytes, the host controller sets the babble detected bit to a one and halts the
Table 13-73. Summary of Transaction Errors
Event/ Result
Queue Head/qTD/iTD/siTD Side Effects
USBSTS[USBERRINT]
Cerr Status Field
CRC –1 XactErr set 1
1
Timeout –1 XactErr set 1
1
Bad PID
2
–1 XactErr set 1
1
Babble N/A See Section 13.6.14.1.2, “Serial Bus Babble” 1
Buffer Error N/A See Section 13.6.14.1.3, “Data Buffer Error”
1
If occurs in a queue head, then USBERRINT is asserted only when Cerr counts down from a one to a
zero. In addition the queue is halted.
2
The host controller received a response from the device, but it could not recognize the PID as a valid PID.