Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-118 Freescale Semiconductor
The initial SplitXState of the first siTD is Do Start Split. The host controller will visit the first siTD eight
times during frame X. The C-mask bits in microframes 0 and 1 are ignored because the state is Do Start
Split. During microframe 4, the host controller determines that it can run a start-split (and does) and
changes SplitXState to Do Complete Split. During microframes 6 and 7, the host controller executes
complete-splits. Notice the siTD for frame X+1 has it's SplitXState initialized to Do Complete Split. As
the host controller continues to traverse the schedule during H-Frame X+1, it will visit the second siTD
eight times. During microframes 0 and 1 it will detect that it must execute complete-splits.
During H-Frame X+1, microframe 0, the host controller detects that siTD
X+1
's Back Pointer[T] bit is a
zero, saves the state of siTD
X+1
and fetches siTD
X
. It executes the complete split transaction using the
transaction state of siTD
X
. If the siTD
X
split transaction is complete, siTD's Active bit is cleared and
results written back to siTD
X
. The host controller retains the fact that siTD
X
is retired and transitions the
SplitXState in siTD
X+1
to Do Start Split. At this point, the host controller is prepared to execute the
start-split for siTD
X+1
when it reaches microframe 4. If the split-transaction completes early
(transaction-complete is defined in Section 13.6.12.3.5, “Periodic Isochronous—Do Complete Split”),
that is, before all the scheduled complete-splits have been executed, the host controller changes
siTD
X
[SplitXState] to Do Start Split early and naturally skips the remaining scheduled complete-split
transactions. For this example, siTD
X+1
does not receive a DATA0 response until H-Frame X+2,
microframe 1.
During H-Frame X+2, microframe 0, the host controller detects that siTD
X+2
's Back Pointer[T] bit is zero,
saves the state of siTD
X+2
and fetches siTD
X+1
. As described above, it executes another split transaction,
receives an MDATA response, updates the transfer state, but does not modify the Active bit. The host
controller returns to the context of siTD
X+2
, and traverses it's next pointer without any state change updates
to siTD
X+2
.
During H-Frame X+2, microframe 1, the host controller detects siTD
X+2
's S-mask[0] bit is zero, saves the
state of siTD
X+2
and fetches siTD
X+1
. It executes another complete-split transaction, receives a DATA0
response, updates the transfer state and clears the Active bit. It returns to the state of siTD
X+2
and changes
its SplitXState to Do Start Split. At this point, the host controller is prepared to execute start-splits for
siTD
X+2
when it reaches microframe 4.
13.6.13 Port Test Modes
EHCI host controllers implement the port test modes Test J_State, Test K_State, Test_Packet, Test
Force_Enable, and Test SE0_NAK as described in the USB Specification Revision 2.0. The required, port
test sequence, assuming the CF-bit in the CONFIGFLAG register is set, is as follows:
1. Disable the periodic and asynchronous schedules by clearing the USBCMD[ASE] and
USBCMD[PSE].
2. Place all enabled root ports into the suspended state by setting the Suspend bit in the PORTSC
register (PORTSC[SUSP]).
3. Clear USBCMD[RS] (run/stop) and wait for USBSTS[HCH] to transition to a one. Note that an
EHCI host controller implementation may optionally allow port testing with RS set. However, all
host controllers must support port testing with RS cleared and HCH set.